1. Field
The present invention relates to a memory arrangement having a controller and having at least one memory device.
2. Background Information
Digital computers such as personal computers, laptops, servers, workstations always contain, in addition to one or more central computers (usually referred to as “processors”), additional electrical functional units that cooperate with the processor as peripheral units. At least one of the peripheral units is also always a memory arrangement having a controller and having at least one memory device. Such a memory arrangement serves to supply the processor with data from the memory device (a so-called read operation, since data are read from memory cells of the memory device) or to store data obtained from the processor in memory cells of the memory device (a so-called write operation, since data are written to memory cells of the memory device).
In order to relieve the burden on the processor, the controller is arranged between the processor and the memory devices. Its purpose is to convert requests received on the part of the processor for the memory devices (e.g. write or read operation, addressing data and memory data) into corresponding signals for the memory devices and also to communicate correspondingly with the memory devices and the processor. Such an arrangement comprising controller and memory devices is referred to as a “memory arrangement” in the present case.
Modern processors have a high operating speed (the operating frequency is in the meantime>2.5 GHz); whereas memory devices such as e.g. of the RAM, ROM or flash type always have a significantly lower operating speed than a modern processor. Therefore, it has always been an aim to design memory arrangements in such a way that an operating speed that is as high as possible can be achieved with them.
It has been shown in the past that, in cases in which a changeover is to be made from a write operation to a read operation, or vice versa, i.e. in which a changeover is to be made from read operation to write operation, it is necessary to accept waiting times that are given under specific addressing conditions before the line system present in the memory devices, in particular, functions properly again. This is caused inter alia by capacitive loading of the line system in the memory devices. Such changeover processes take place relatively frequently: the operation of a memory arrangement is usually made up of approximately 70% reading operation (i.e. read accesses are made to the memory cells of the memory devices) and approximately 30% writing operation (i.e. data are written to the memory cells of the memory devices). Consequently, the waiting times described slow down the maximum possible operating speed of the entire memory arrangement.